Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. Most common among these are metal-oxide-semiconductor field-effect transistors (MOSFETs), wherein a gate electrode is energized to create an electric field in a channel region of a semiconductor body, by which electrons are allowed to travel through the channel between a source region and a drain region of the semiconductor body. The source and drain regions are typically formed by adding dopants to targeted regions on either side of the channel. A gate dielectric or gate oxide is formed over the channel, and a gate electrode or gate contact is formed over the gate dielectric. The gate dielectric and gate electrode layers are then patterned to form a gate structure overlying the channel region of the substrate.
In operation of the resulting MOS transistor, the threshold voltage (Vt) is the gate voltage value required to render the channel conductive by formation of an inversion layer at the surface of the semiconductor channel. Complimentary MOS (CMOS) devices have become widely used in the semiconductor industry, wherein both n-channel and p-channel (NMOS and PMOS) transistors are used to fabricate logic and other circuitry. For enhancement-mode (e.g., normally off) devices the threshold voltage Vt is positive for NMOS and negative for PMOS transistors. The threshold voltage is dependent upon the flat-band voltage, where the flat-band voltage depends on the work function difference between the gate and the substrate materials, as well as on surface charge.
The work function of a material is a measure of the energy required to move an electron in the material outside of a material atom from the Fermi level, and is usually expressed in electron volts (eV). For CMOS products, it is desirable to provide predictable, repeatable, and stable threshold voltages (Vt) for the NMOS and PMOS transistors. To establish Vt values, the work functions of the PMOS and NMOS gate contact and the corresponding channel materials are independently tuned or adjusted through gate and channel engineering, respectively.
Gate stack engineering is employed to adjust the work function of the gate contact materials, where different gate work function values are set for PMOS and NMOS gates. The need to independently adjust PMOS and NMOS gate work functions has made polysilicon attractive for use as a gate contact material in CMOS processes, since the work function of polysilicon can be easily raised or lowered by doping the polysilicon with p-type or n-type impurities, respectively. The PMOS polysilicon gates are typically doped with p-type impurities and NMOS gate polysilicon is doped with n-type dopants, typically during implantation of the respective source/drain regions following gate patterning. In this way, the final gate work functions are typically near the Si conduction band edge for NMOS and near the valence band edge for PMOS. The provision of dopants into the polysilicon also has the benefit of increasing the conductivity of the gate electrode. Polysilicon has thus far been widely used in the fabrication of CMOS devices, wherein the gate engineering provides a desired gate electrode conductivity (e.g., sheet resistance value) by conventional tuning (e.g., implants), and the threshold voltage fine tuning is achieved by tailoring the channel doping level through the Vt adjust implants.
FIG. 1 illustrates a conventional CMOS fabrication process 10 beginning at 12, in which front end processing is performed at 14, including well formation and isolation processing. At 16 and 18, channel engineering is performed (e.g., Vt adjust, punch-thru, and channel stop implants) for PMOS and NMOS regions, respectively. A thin gate dielectric and an overlying polysilicon layer are formed at 20 and 22, respectively, and the polysilicon is patterned at 24 to form gate structures for the prospective NMOS and PMOS transistors. The gate structures are then encapsulated at 26, typically through oxidation, and highly-doped drain (HDD) implants are performed at 28 to provide p-type dopants to prospective source/drains of the PMOS regions and n-type dopants to source/drains of the NMOS regions, using the patterned gate structures and isolation structures as an implantation mask. Sidewall spacers are then formed at 30 along the lateral sidewalls of the gate structures.
At 32, the PMOS source/drain regions and the PMOS polysilicon gate structures are implanted with p-type dopants to further define the PMOS source/drains, and to render the PMOS gates conductive. Similarly, the NMOS source/drain regions and the NMOS polysilicon gate structures are implanted at 34 with n-type dopants, further defining the NMOS source/drains and rendering the NMOS gates conductive. Thereafter, the source/drains and gates are silicided at 36 and back end processing (e.g., interconnect metalization, etc.) is performed at 38, before the process 10 ends at 40. In the conventional process 10, the channel engineering implants at 16 and 18 shift the Vt of the PMOS and NMOS channel regions, respectively, to compensate for the changes in the PMOS and NMOS polysilicon gate work functions resulting from the source/drain implants at 32 and 34, respectively. In this manner, the desired work function difference between the gates and channels may be achieved for the resulting PMOS and NMOS transistors, and hence the desired threshold voltages.
The gate dielectric or gate oxide between the channel and the gate electrode is an insulator material, typically SiO2 or other dielectric, that operates to prevent current from flowing from the gate electrode into the channel when a voltage is applied to the gate electrode. The gate dielectric also allows an applied gate voltage to establish an electric field in the channel region in a controllable manner. Continuing trends in semiconductor product manufacturing include reduction in electrical device feature sizes (scaling), as well as improvements in device performance in terms of device switching speed and power consumption. MOS transistor performance may be improved by reducing the distance between the source and the drain regions under the gate electrode of the device, known as the gate or channel length, and by reducing the thickness of the layer of gate dielectric that is formed over the semiconductor surface.
However, there are electrical and physical limitations on the extent to which SiO2 gate dielectrics can be made thinner. These include gate leakage currents tunneling through the thin gate oxide, limitations on the ability to form very thin oxide films with uniform thickness, and the inability of very thin SiO2 gate dielectric layers to prevent dopant diffusion from the gate polysilicon into the underlying channel. Accordingly, recent scaling efforts have focused on high-k dielectric materials having dielectric constants greater than that of SiO2, which can be formed in a thicker layer than scaled SiO2, and yet which produce equivalent field effect performance. A thicker high-k dielectric layer can thus be formed to avoid or mitigate tunneling leakage currents, while still achieving the required electrical performance equivalent (e.g., capacitance value) to a thinner SiO2.
It has also been proposed to utilize hafnium-based high k dielectric materials in combination with a lanthaide series metal to lower the work function of metal gates. The lanthaide series metal is provided as a distinct surface layer over the high k dielectric material. This proposal, however, increases the overall equivalent oxide thickness (EOT) of the layer of gate oxide.
Another shortcoming of scaled CMOS devices having polysilicon gate contacts is known as polysilicon depletion. Polysilicon depletion occurs when annealing or other thermal back-end processing following the implants at 32 and 34 is insufficient to drive enough implanted impurities down the entire depth of the polysilicon gate structures. In this situation, with this limited doping concentration and under the proper biasing of the gate, a bottom portion of the polysilicon gate contact near the gate dielectric is “depleted” of charges, and acts as an insulator. The depleted portion of the gate contact and the gate dielectric operate as series connected capacitors, resulting in a reduced effective gate capacitance, which reduces the drive current capability of the device. Consequently, polysilicon depletion causes reduction in device performance which leads to poor unscalable devices. Simply increasing the implant energy and/or anneal time to combat poly depletion has adverse results, in that the corresponding depths of the concurrently implanted source/drain regions are increased.
With the relatively thick gate dielectrics and gate electrode structures of the past, poly depletion was not critical to ensuring desired device performance. However, as gate dielectrics and gate electrodes continue to become smaller through scaling, the polysilicon depletion problem is more pronounced, wherein polysilicon depletion regions of 3 to 4 angstroms become a significant fraction of the overall effective gate thickness. Thus, while polysilicon gate electrodes have previously offered flexibility in providing dual work functions at the band edges for CMOS processes, the future viability of conventional polysilicon gate technology is lessened as scaling efforts continue. Accordingly, attention has recently been directed again to the possibility of using metal gate electrodes in CMOS products. There remains a need for dual or differentiated work function capability (e.g., for PMOS and NMOS transistors) in CMOS processes. In this regard, metal work functions are not shifted as easily by the same amounts as was the case for polysilicon. Accordingly, there is a need for improved CMOS transistor gate designs and fabrication techniques by which the benefits of scaling can be achieved while avoiding or mitigating the poly depletion degradation found in conventional devices and without increasing EOT.